A number of memory devices, such as flash memory devices, use analog memory cells to store data. Each memory cell stores an analog value, also referred to as a storage value. The storage value represents the information stored in the cell. In flash memory devices, for example, each analog memory cell typically stores a certain voltage. The range of possible analog values for each cell is typically divided into threshold regions, with each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired one or more bits.
Single-level cell (SLC) flash memory devices, for example, store one bit per memory cell (or two possible memory states). Multi-level cell (MLC) flash memory devices, on the other hand, store two or more bits per memory cell (i.e., each cell has four or more programmable states). In a multi-level cell device, at least three threshold levels are employed to define four or more different threshold states. The operating range of an individual cell is thus divided into an increased number of states and the range of each state is smaller than for a single-level cell device. Thus, the reliability of any single bit in a multi-level cell device is generally lower than the reliability of a single-level cell device.
For a more detailed discussion of multi-level codes, see, for example, U. Wachsmann et al., “Multilevel Codes: Theoretical Concepts and Practical Design Rules,” IEEE Trans. on Information Theory, Vol. 45, No. 5, 1361-91 (1999), incorporated by reference herein.
A flash memory typically comprises a flash memory array, flash controller and an interface for communications between the flash memory array and the flash controller. The Open NAND Flash Interface Working Group (ONFI) is an industry consortium developing open standards for NAND flash memory devices and devices that communicate with them. ONFI has produced a specification for a standard interface to NAND flash chips. ONFI Version 2.0 uses Double Data Rate (DDR) techniques to transfer data on both the rising and falling edges of the clock signal. While ONFI Version 2.0 has increased the data-carrying capacity of the NAND flash interface, it does not provide additional bandwidth for carrying additional information that may improve performance.
A need therefore exists for an improved interface between the controller and the memory array in a flash memory device. Yet another need exists for an improved interface between the controller and the memory array in a flash memory device that provides additional bandwidth for additional information about the transmitted data. A further need exists for an improved interface between the controller and the memory array in a flash memory device that provides additional bandwidth without significantly increasing power dissipation or surface area.